A phase-locked loop (PLL) compares the phase difference between a reference clock signal and a feedback clock signal and adjusts the frequency of the feedback clock signal to synchronize the clock signals. The frequency of the feedback clock signal locks to the frequency of the reference clock signal. Various circuits exist for determining when the clock signals are locked. A conventional way to determine when a feedback clock signal is locked to a reference clock signal involves counting the cycles of the feedback clock signal during the time it takes to count a predetermined number of cycles of the reference clock signal. The feedback clock signal and the reference clock signal are considered to be locked when the difference between the cycle count of the feedback clock signal and the predetermined number of cycles of the reference clock signal falls within a desired range.
FIG. 1 (prior art) illustrates a conventional lock detector 10 operatively associated with a phase-locked loop (PLL) 11. PLL 10 includes a phase detector 12, a charge pump 13, a loop filter 14, a voltage-controlled oscillator (VCO) 15 and a frequency divider 16. Phase detector 12 compares the phase of a feedback clock signal (FBCKL) 17 to the phase of a reference clock signal (REFCLK) 18. Depending on the phase difference, phase detector 12 outputs up and down control signals causing charge pump 13 to add charge to and subtract charge from its output lead. The voltage on the output lead of charge pump 13, after being filtered by loop filter 14, becomes the control voltage for VCO 15. VCO 15 outputs an output clock signal 19 having a higher frequency when the control voltage increases and a lower frequency when the control voltage decreases. Frequency divider 16 receives output clock signal 19, divides signal 19 down to a lower frequency, and outputs FBCKL 17.
Lock detector 10 includes a feedback latch 20, a reference latch 21, a feedback counter 22, a reference counter 23 and a match detector 24. Feedback latch 20 receives FBCLK 17 and outputs an indication of each rising edge of FBCLK 17. Feedback counter 22 counts the number of rising edges indicated by feedback latch 20 and sends count signals indicative of the current total count to match detector 24. Reference latch 21 receives REFCLK 18 and outputs an indication of each rising edge of REFCLK 18. Reference counter 23 receives the output of reference latch 21 and counts the number of rising edges up to a predetermined number. When the count reaches the predetermined number, reference counter 23 sends a freeze signal to match detector 24. At the moment match detector 24 receives the freeze signal, match detector 24 determines the difference between the current total count indicated by the last count signal and the predetermined number counted by reference counter 23.
Match detector 24 outputs a lock detect signal 25 indicating whether FBCLK 17 is locked to REFCLK 18, and by inference indicating that PLL output clock signal 19 is an exact, predefined, multiple of REFCLK 18. For example, lock detect signal 25 can be a digital one indicating “lock” or a digital zero indicating “out of lock.” Where reference counter 23 is set to count eighteen cycles of REFCLK 18, match detector 24 outputs signal 25 indicating “lock” when seventeen, for example, is the value of the last count signal received from feedback counter 22 immediately prior to receiving a freeze signal from reference counter 23. Match detector 24 outputs signal 25 indicating “out of lock” when feedback counter 22 counts, for example, sixteen cycles of FBCLK 17 during the time it takes for reference counter 23 to count eighteen cycles of REFCLK 18. Thus, in this example, lock detector 10 indicates that FBCLK 17 is locked to REFCLK 18 when the average frequency of FBCLK 17 varies by less than 2/18ths of the frequency of REFCLK 18.
FIG. 2 (prior art) illustrates a shortcoming of lock detector 10. Lock detector 10 indicates that two signals are locked based on the average number of rising edges of those signals over a period of time, even where those signals have different frequencies during portions of that period of time. Over a first time period 26, lock detector 10 indicates that FBCLK 17 and REFCLK 18 are locked. During the beginning and end portions of time period 26, however, FBCLK 17 has a lower frequency than REFCLK 18. During the middle portion, FBCLK 17 has a higher frequency. If data is transmitted on PLL output clock signal 19 because lock detector 10 indicates that FBCLK 17 and REFCLK 18 are locked, the fluctuations in frequency of FBCLK 17, and therefore of the frequency of output clock signal 19, can cause unreliable data transmission. Lock detector 10 also indicates that FBCLK 17 and REFCLK 18 are locked over a second time period 27 (and by inference that the PLL output clock signal 19 is an exact, predefined and stable multiple of REFCLK 18), even though the frequency of FBCLK 17 (and therefore output clock signal 19) is not stable over the second time period 27.
Because only average frequencies of clock signals are compared, the reference and feedback clock signals are counted for a relatively long period of time to increase the probability that the feedback clock signal is stable and, therefore, truly locked. The predetermined count number of reference clock cycles is typically much greater than eighteen and can undesirably delay circuit startup time. Thus, lock detector 10 reliably indicates whether two signals are locked only after the relatively long period of time, for example, five hundred twelve reference clock cycles. Moreover, where lock detector 10 counts for five hundred twelve cycles of REFCLK 18, both reference counter 23 and feedback counter 22 are physically large counter circuits that occupy valuable space on a semiconductor die.
A circuit is thus desired that detects when two clock signals are locked and does not indicate frequency lock based on the average frequency of each clock signal over a period of time.